CS5509-ASZR【PDF 7/24 页】IC ADC 16BIT SGL SUPP 16-SOIC

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CS5509

DS125F3

to prevent aliasing. Spectral components greater

than one half the output word rate on the VREF in-

puts (VREF+ and VREF-) may also be aliased. Fil-

tering of the reference voltage to remove these

spectral components from the reference voltage is

desirable.

Crystal Oscillator

The CS5509 is designed to be operated using a

32.768kHz "tuning fork" type crystal. One end of

the crystal should be connected to the XIN input.

The other end should be attached to XOUT. Short

lead lengths should be used to minimize stray ca-

pacitance.

Over the industrial temperature range (-40 to

+85 °C) the on-chip gate oscillator will oscillate

with other crystals in the range of 30kHz to 53 kHz.

The chip will operate with external clock frequen-

cies from 30kHz to 330kHz over the industrial tem-

perature range. The 32.768 kHz crystal is normally

specified as a time-keeping crystal with tight spec-

ifications for both initial frequency and for drift

over temperature. To maintain excellent frequency

stability, these crystals are specified only over lim-

ited operating temperature ranges (i.e. -10 °C to

+60 °C) by the manufacturers. Applications of

these crystals with the CS5509 does not require

tight initial tolerance or low tempco drift. There-

fore, a lower cost crystal with looser initial toler-

ance and tempco will generally be adequate for use

with the CS5509. Also check with the manufactur-

er about wide temperature range application of

their standard crystals. Generally, even those crys-

tals specified for limited temperature range will op-

erate over much larger ranges if frequency stability

over temperature is not a requirement. The frequen-

cy stability can be as bad as ±3000 ppm over the

operating temperature range and still be typically

better than the line frequency (50 Hz or 60Hz) sta-

bility over cycle-to-cycle during the course of a

day.

Serial Interface Logic

The digital filter in the CS5509 takes 1624 clock

cycles to compute an output word once a conver-

sion begins. At the end of the conversion cycle, the

filter will attempt to update the serial port. Two

clock cycles prior to the update DRDY will go

high. When DRDY goes high just prior to a port up-

date it checks to see if the port is either empty or

unselected (CS = 1). If the port is empty or unse-

lected, the digital filter will update the port with a

new output word. When new data is put into the

port DRDY will go low.

Reading Serial Data

SDATA is the output pin for the serial data. When

CS goes low after new data becomes available

(DRDY goes low), the SDATA pin comes out of

Hi-Z with the MSB data bit present. SCLK is the

input pin for the serial clock. If the MSB data bit is

on the SDATA pin, the first rising edge of SCLK

enables the shifting mechanism. This allows the

falling edges of SCLK to shift subsequent data bits

out of the port. Note that if the MSB data bit is out-

put and the SCLK signal is high, the first falling

edge of SCLK will be ignored because the shifting

mechanism has not become activated. After the

first rising edge of SCLK, each subsequent falling

edge will shift out the serial data. Once the LSB is

present, the falling edge of SCLK will cause the

SDATA output to go to Hi-Z and DRDY to return

high. The serial port register will be updated with a

new data word upon the completion of another con-

version if the serial port has been emptied, or if the

CS is inactive (high).

CS can be operated asynchronously to the DRDY

signal. The DRDY signal need not be monitored as

long as the CS signal is taken low for at least two

XIN clock cycles plus 200ns prior to SCLK being

toggled. This ensures that CS has gained control

over the serial port.

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